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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Document Title
2Mx16 bit CellularRAM AD-MUX
Revision History
Revision No.
0.0
History
Initial Draft
Draft Date
July 18,2007
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com 1 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
x16 Burst, Multiplexed Address/Data
FEATURES
- 16-bit multiplexed address/data bus - Sigle device supports asynchrous and burst operation - Vcc, VccQ voltages: 1.7V~1.95V VCC 1.7V~1.95V VCCQ - Random access time: 70ns - Burst mode READ and WRITE access: 4, 8, 16, or 32 words, or continuous burst Burst wrap or sequential Max clock rate: 104 MHz (tCLK = 9.62ns) , 133MHz(tCLK = 7.5ns) Burst initial latency: 38.5ns (4 clocks) @ 104 MHz , 37.5ns(5 clocks) @ 133 MHz tACLK: 7ns @ 104 MHz , 5.5ns @ 133 MHz - Low power consumption: Asynchronous READ: <25mA Initial access, burst READ: (38.5ns [4 clocks] @ 104 MHz) <35mA Continuous burst READ: <30mA Initial access, burst READ: (37.5ns [5 clocks] @ 133 MHz) <40mA Continuous burst READ: <35mA - Low-power features On-chip temperature compensated self refresh (TCSR) Partial array refresh (PAR) - Operating temperature range: Wireless -30C to +85C
OPTIONS
- Configuration: 32Mb (2 megabit x 16) - Vcc core / VccQ I/O voltage supply: 1.8V - Timing: 70ns access - Frequency: 83 MHz, 104 MHz, 133 MHz - Standby current at 85C Low Low Power : 100A(max) Low Power : 120A(max) Standard : 140A(max)
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table of Contents
Features.................................................................................................................................................................................. Options............................................................................................................................................................................... General Description................................................................................................................................................................. Functional Description............................................................................................................................................................. Power-Up Initialization........................................................................................................................................................ Bus Operating Modes.............................................................................................................................................................. Asynchronous Mode........................................................................................................................................................... Burst Mode Operation......................................................................................................................................................... Mixed-Mode Operation ....................................................................................................................................................... WAIT Operation ................................................................................................................................................................. LB# / UB# Operation........................................................................................................................................................... Low-Power Operation......... .................................................................................................................................................... Standby Mode Operation ................................................................................................................................................... Temperature Compensated Refresh................................................................................................................................... Partial Array Refresh .......................................................................................................................................................... Registers................................................................................................................................................................................. Access Using CRE ............................................................................................................................................................. Software Access ................................................................................................................................................................ Bus Configuration Register................................................................................................................................................. Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................................... Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................................ Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ........................................................................... WAIT Polarity (BCR[10]) Default = WAIT Active HIGH................................................................................................... Initial Access Latency (BCR[14]) Default = Variable....................................................................................................... Operating Mode (BCR[15]) Default = Asynchronous Operation..................................................................................... Refresh Configuration Register........................................................................................................................................... Device Identification Register.............................................................................................................................................. Electrical Characteristics......................................................................................................................................................... Timing Requirements.............................................................................................................................................................. Timing Diagrams..................................................................................................................................................................... 2 2 6 9 9 10 10 12 15 15 15 16 16 16 16 17 17 21 23 24 24 25 26 26 28 28 29 30 32 36
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Functional Block Diagram - 2 Meg x 16 ......................................................................................... Power-Up Initialization Timing .......................................................................................................... READ Operation ............................................................................................................................... WRITE Operation ............................................................................................................................. Burst Mode READ (4-word burst)...................................................................................................... Burst Mode WRITE (4-word burst).................................................................................................... Refresh Collision During Variable-Latency READ Operation ........................................................... Wired-OR WAIT Configuration ......................................................................................................... Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ......... Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ........... Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ................................. Register READ, Synchronous Mode, Followed by READ ARRAY Operation ................................... Load Configuration Register ............................................................................................................. Read Configuration Register ............................................................................................................ Bus Configuration Register Definition ............................................................................................... WAIT Configuration During Burst Operation ..................................................................................... Latency Counter (Variable Initial Latency, No Refresh Collision) ...................................................... Latency Counter (Fixed Latency) ..................................................................................................... Refresh Configuration Register Mapping ......................................................................................... AC Input / Output Reference Waveform ........................................................................................... AC Output Load Circuit .................................................................................................................... Initialization Period .......................................................................................................................... Asynchronous READ ....................................................................................................................... Single-Access Burst READ Operation - Variable Latency ................................................................ 4-Word Burst READ Operation - Variable Latency ........................................................................... Single-Access Burst READ Operation - Fixed Latency .................................................................... 4-Word Burst READ Operation - Fixed Latency ............................................................................... Burst READ Terminate at End-of-Row (Wrap off) ............................................................................. Burst READ Row Boundary Crossing .............................................................................................. Asynchronous WRITE ..................................................................................................................... Burst WRITE Operation - Variable Latency Mode ............................................................................ Burst WRITE Operation - Fixed Latency Mode ................................................................................ Burst WRITE Terminate at End-of-Row (Wrap off) ........................................................................... Burst WRITE Row Boundary Crossing ............................................................................................ Burst WRITE Followed by Burst READ ............................................................................................ Asynchronous WRITE Followed by Burst READ .............................................................................. Burst READ Followed by Asynchronous WRITE .............................................................................. Asynchronous WRITE Followed by Asynchronous READ ............................................................... 6 9 11 11 12 13 14 15 17 18 19 20 22 22 23 26 27 27 28 31 31 36 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Signal Descriptions ........................................................................................................................................... Bus Operations ................................................................................................................................................. Sequence and Burst Length .............................................................................................................................. Drive Strength ................................................................................................................................................... Variable Latency Configuration Codes............................................................................................................... Fixed Latency Configuration Codes................................................................................................................... Address Patterns for PAR(RCR[4] =1)............................................................................................................... Device Identification Register Mapping ............................................................................................................. Absolute Maximum Ratings ............................................................................................................................... Electrical Characteristics and Operating Conditions ......................................................................................... Capacitance ...................................................................................................................................................... Asynchronous READ Cycle Timing Requirements ............................................................................................ Burst READ Cycle Timing Requirements ......................................................................................................... Asynchronous WRITE Cycle Timing Requirements .......................................................................................... Burst WRITE Cycle Timing Requirements ......................................................................................................... Initialization Timing Parameters ........................................................................................................................ 7 8 24 25 26 27 29 29 30 30 31 32 33 34 35 36
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
GENERAL DESCRIPTION
32Mb CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 32Mb CellularRAM device has a DRAM core organized as 2 Meg x 16 bits. These devices are a variation of the industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality dramatically reduce the required signal count, and increases read/write bandwidth. For seamless operation on a burst Flash bus, 32Mb CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user accessible control registers define device operation. The bus configuration register (BCR) defines how the 32Mb CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. 32Mb CellularRAM products include two mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated self refresh (TCSR) uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower temperatures to minimize current consumption during standby. The system configurable refresh mechanisms are accessed through the RCR. This 32Mb CellularRAM specification defines the industry-standard CellularRAM1.5 x16 A/D Mux feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, a variety of wrap options, and a device ID register (DIDR). Figure 1: FUNTIONAL BLOCK DIAGRAM - 2 meg x 16
A[20:16]
Address Decode Logic
Refresh Configuration Register (RCR)
2,048K x 16 DRAM MEMORY ARRAY
Input Output MUX and Buffers
A/DQ[7:0] A/DQ[15:8]
Device ID Register (DIDR)
Bus Configuration Register (BCR) CLK CE# WE# OE# ADV# CRE LB# UB# WAIT
Control Logic Internal External
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed information.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 1: SIGNAL DESCRIPTIONS Symbol Type Descriptions Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE operations when burst mode is enabled. Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during asynchronous READ and WRITE operations. Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access the RCR, BCR, or DIDR. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower byte enable. DQ[7:0] Upper byte enable. DQ[15:8]
A[20:16]
Input
CLK (note1)
Input
ADV# (note1) CRE
Input
Input
CE#
Input
OE#
Input
WE# LB# UB#
Input Input Input
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins A/DQ[15:0] Input/Output behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address, RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH. Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z when CE# is HIGH. Reserved for future use. Device power supply: (1.70V.1.95V) Power supply for device core operation. I/O power supply: (1.70V.1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground.
WAIT (note1)
Output
RFU VCC VCCQ VSS VSSQ
Supply Supply Supply Supply
Note: 1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 2: BUS OPERATIONS Asynchfonous Mode BCR[15]=1 Read Write Standby No operation Configuration register write Configuration register read Burst Mode BCR[15]=0 Async read Async write Standby No operation Initial burst read Initial burst write Power Active Active Standby Idle Active CLK ADV# CE# X X H or L X X X X L L H L L OE# L X X X H WE# H L X X L CRE L L L L H UB#/ LB# L L X X X WAIT2 Low-z High-z High-z Low-z Low-z DQ[15:0] Data out Data in High-z X High-z Config. Reg.out DQ[15:0] Data out Data in High-z X Address Address Data out or Data in High-z Config. Reg.out Notes 4, 7 4 5, 6 4, 6 4, 8 4, 8 Notes 4 4 5, 6 4, 6
Active
X
L
L
H
H
L UB#/ LB# L L X X L X
Low-z
Power Active Active Standby Idle Active Active
CLK ADV# CE# H or L H or L H or L H or L X X L L L L H L L L
OE# L X X X X H
WE# H L X X H L
CRE L L L L L L
WAIT Low-z Low-z High-z Low-z Low-z Low-z
Burst continue
Active
H
L
X
X
X
L
Low-z
4, 8
Configuration register write Configuration register read
Active
L
L
H
L
H
X
Low-z
8, 9
Active
L
L
L
H
H
L
Low-z
8, 9
Note: 1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power during standby mode. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are enabled. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current. 7. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT).
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
FUNTIONAL DESCRIPTION
In general, 32Mb CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The 32Mb device contains a 33,554,432-bit DRAM core, organized as 2,097,152 addresses by 16 bits.The device implement a multiplexed address/data bus. This multiplexed configuration supports greater bandwidth through the x16 data bus, yet still reduces the required signal count. The 32Mb CellularRAM bus interface supports both asynchronous and burst mode transfers.
POWER-UP INITIALIZATION
32Mb CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. Until the end of tPU, CE# should track VccQ and remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 2: Power-Up Initialization Timing
Vcc=1.7V
t
Vcc VccQ
PU
Device Initialization
Device ready for normal operation
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
BUS OPERATING MODES
32Mb CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR.
Asynchronous Mode
Asynchronous mode uses the industry- standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations(Figure 3) are initiated by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address onto the A/ DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations(Figure 4 ) occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW. with the address on the A/DQ bus. ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#; however, OE# must be HIGH while the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever occurs first). During asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 3: READ Operation
Valid Address
A[20:16] CE#
OE# WE# A/DQ[15:0] Valid Address
High-Z
Valid Data
ADV#
LB#/UB# Don't Care
Figure 4: WRITE Operation
A[20:16] CE#
Valid Address
OE# WE# A/DQ[15:0] Valid Address
tCEM
Valid Data
ADV# LB#/UB# Don't Care Undefined
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 5) or WRITE (WE# = LOW, Figure 6). Figure 5: Burst Mode READ (4-word burst)
CLK
A[20:16]
Address
Address
ADV#
Latency Code 2(3 clocks)
CE#
OE#
WE#
LB#/UB#
A/DQ[15:0]
Address
D0
D1
D2
D3
Address
WAIT
READ Burst Identified (WE# = HIGH)
READ Burst Identified (WE# = HIGH) Don't Care Undefined
Note: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 6: Burst Mode WRITE (4-word burst, OE# HIGH)
CLK
A[20:16]
Address
Address
ADV#
Latency Code 2(3 clocks)
CE#
WE#
LB#/UB#
A/DQ[15:0]
Address
D0
D1
D2
D3
Address
WAIT
WRITE Burst Identified (WE# = LOW)
WRITE Burst Identified (WE# = LOW) Don't Care
Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the address. It goes back to the first address and continues to burst when continuous bursts meet the end of address. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the CellularRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length. With wrap off, the CellularRAM device will restore the previous row's data and access the next row, WAIT will be de-asserted, and the burst can continue across the row boundary(See Figeure 29 for a READ, Figure 34 for a WRITE). If the burst is to terminate at the row boundary, CE# must go HIGH within 2 clocks of the last data(See Figure 28). CE# must go HIGH before any clock edge following the last word of a defined-length burst WRITE(See Figure 31 and 32). The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 7: Refresh Collision During Variable-Latency READ Operation
CLK
VIH VIL VIH VIL VIH VIL VIH
A[20:16]
Valid Address
ADV#
CE#
VIL VIH
OE#
VIL VIH VIL VIH VIL VOH VOL VOH VOL High-Z
WE#
LB#/UB#
A/DQ[15:0]
Valid Address
VOH VOL
D0
D1
D2
D3
WAIT
Additional WAIT states inserted to allow refresh completion. Don't Care Note: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Undefined
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target address. CE# can remain LOW when the device is transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 36 on page 49 for the "Asynchronous WRITE Followed by Burst READ" timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal(See Figure 8). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 8: Wired or WAIT Configuration
CellularRAM
WAIT READY WAIT Processor Other Device WAIT Other Device
External Pull-Up Pull-Down Resistor
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For burst READ operations, WAIT will remain active until valid data is output from the device. For burst WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed(See Figure 7 ). When the refresh operation has completed, the burst READ operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed. WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during asynchronous WRITE operations. WAIT should be ignored during all asynchronous operations. By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of the row. If WAIT is not monitored, the controller must properly terminate all burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
LOW-POWER OPERATION
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually monitors the temperature to select an appropriate self-refresh rate.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map(See Table 7). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH(see Figure 9 through 12 on pages 17 through 20) . When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[20:16] and A/DQ[15:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care". The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For READs, address inputs other than A[19:18] are "Don't Care", and register bits 15:0 are output on DQ[15:0]. Immediately after a configuration register READ or WRITE operation is performed, reading the memory array is highly recommended. Figure 9: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
A[20:16] (except A[19:18]) OPCODE tAVS
Select control register
Address tAVH Address
A[19:18]1
CRE
tAVS tAVH
ADV# tVP CE#
Initiate Control register access
tCPH
tCW OE# tWP WE#
Write address bus value to control register
LB#/UB#
A/DQ[15:0]
OPCODE
Address
Valid data
Don't Care
Note: A[19:18] = 00b to load RCR, and 10b to load BCR.
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[20:16] (except A[19:18])
OPCODE tSP tHD
Latch control register address
Address
A[19:18]
2
Address tSP tHD
CRE tSP ADV# tCBPH
Note3
tHD
tCSP CE#
OE# tSP WE# tHD
LB#/UB#
A/DQ[15:0]
OPCODE
Address
Valid data
tKHTL WAIT
High-Z High-Z
Don't Care Note: 1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
18
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation
A[20:16] (except A[19:18]) tAVS Select register A[19:18]1 tAA CRE tAVS tAA ADV# tVP CE# tCPH tAADV tCPH tAVH tAVH
Address
Address
Initiate register access tCO tHZ
OE# tOE WE# tBA tOLZ LB#/UB# tBHZ tOHZ
A/DQ[15:0]
Valid CR
Address
Valid data
Don't Care
Undefined
Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
19
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[20:16] (except A[19:18]) tSP A[19:18]
2
Address tHD
Latch control register address
Address tSP tHD
CRE tSP ADV# tABA
Note3
tHD tCBPH
tCSP CE#
tHZ OE# tOHZ
WE# tSP LB#/UB# tOLZ A/DQ[15:0] tACLK tKOH Address Valid data tBOE tHD
Valid CR
tKHTL WAIT
High-Z High-Z
Don't Care
Undefined
Note: 1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
20
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 13 ). The READ sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 14). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (1FFFFFh); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. This value must be valid at the falling edge of WE#. During the fourth operation, DQ[15:0] transfer data in to or out of bits 15:0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required.
21
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 13: Load Configuration Register
CE#
READ
READ
WRITE
WRITE
OE#
WE#
LB#/UB#
ADV#
A[20:16]
Address (MAX) Address XXXX (MAX)
Address (MAX) Address (MAX) XXXX
Address (MAX) Address (MAX) RCR : 0000h BCR : 0001h
Address (MAX)
0ns (min); Note 1
A/DQ[15:0]
Address (MAX)
CR Value in Don't Care
Note: If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
Figure 14: Read Configuration Register
CE#
READ
READ
WRITE
READ
OE#
WE#
LB#/UB#
ADV#
A[20:16]
Address (MAX) Address XXXX (MAX)
Address (MAX) Address (MAX) XXXX
Address (MAX) Address (MAX) RCR : 0000h BCR : 0001h DIDR : 0002h
Address (MAX)
0ns (min); Note 1
A/DQ[15:0]
Address (MAX)
CR Value out Don't Care
Note: If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
22
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
BUS CONFIGURATION REGISTER
The BCR defines how the CellularRAM device interacts with the system memory bus. Figure 15 describes the control bits in the BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software sequence with A/DQ = 0001h on the third cycle. Figure 15: Bus Configuration Register Definition
A [20] A [19:18] A [17:16] A/DQ 15 A/DQ 14 A/DQ [13:11] A/DQ 10 A/DQ 9 A/DQ 8 A/DQ 7 A/DQ 6 A/DQ [5:4] A/DQ 3 A/DQ [2:0]
20
19-18
17-16
15
14
13
12 Latency Counter
11
10
9
8
7
6
5
4
3
2
1
0
Register Reserved Select
All must be set to "0"
Operating Initial Reserved Mode Latency
WAIT WAIT Drive Burst Reserved Reserved Reserved Polarity Configuration(WC) Strength Wrap(BW)
Must be set to "0" Must be set to "0" Must be set to "0"
Burst Length(BL)
Must be set to "0"
BCR[14] 0 1
Initial Access Latency Variable (default) Fixed
BCR[3] 0 1
Burst Wrap (Note 1) Burst wraps within the burst length Burst no wrap (default) Drive Strength Full 1/2 (default) 1/4 Reserved
BCR[5] BCR[4] BCR[13] BCR[12] BCR[11] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Latency Counter Code 8 Code 1 - Reserved Code 2 Code 3 (default) Code 4 Code 5 Code 6 Code 7 - Reserved BCR[10] 0 1 BCR[15] 0 1 Operating Mode Synchronous burst access mode Asynchronous access mode (default) WAIT Polarity Active LOW Active HIGH (default) BCR[8] 0 1 0 0 1 1 0 1 0 1
WAIT Configuration
Asserted during delay Asserted one data cycle before delay (default)
BCR[2] BCR[1] BCR[0] 0 0 0 1 1 0 1 1 0 1 Others 1 0 1 0 1
Burst Length (Note 1) 4 words 8 words 16 words 32 words Continuous burst (default) Reserved
BCR[19] BCR[18] Register Select 0 1 0 0 0 1 Select RCR Select BCR Select DIDR
Note: 1. Burst wrap and length apply to both READ and WRITE operations. 2. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionallity. BCR[15:0] will be read back as written.
23
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4, 8, 16, or 32 word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to address boundaries; the internal address wrap to 000000h if the device is read past the last address.
Table 3: Sequence and Burst Length BURST Wrap Starting Address 4 Word 8 Word Burst Burst Length Length Linear
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
16 Word Burst Length Linear
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
32 Word Burst Length Linear
0-1-2 ... 29-30-31 1-2-3 ... 30-31-0 2-3-4 ... 31-0-1 3-4-5 ... 0-1-2 4-5-6 ... 1-2-3 5-6-7 ... 2-3-4 6-7-8 ... 3-4-5 7-8-9 ... 4-5-6 ... 14-15-16-...-11-12-13 15-16-17...-12-13-14 ... 30-31-0-...-27-28-29 31-0-1-... -28-29-30
Continuous Burst Linear
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ... 30-31-32-33-34-... 31-32-33-34-35-... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ... 30-31-32-33-34-35-36-... 31-32-33-34-35-36-37-...
BCR[3] Wrap Decimal
0 1 2 3 4 5 6
Linear
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0
Yes
7 ... 14 15 ... 30 31 0 1 2 3 4 5 6 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-1213 7-8-9-10-11-12-1314
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21 7-8-9-10-11-12-13-14-15-16-17-18-19-20-2122 ... 14-15-16-17-18-...-23-24-25-26-27-28-29 15-16-17-18-19-...-24-25-26-27-28-29-30
0-1-2-...-29-30-31 1-2-3-...-30-31-32 2-3-4-...-31-32-33 3-4-5-...-32-33-34 4-5-6-...-33-34-35 5-6-7-...-34-35-36 6-7-8-...-35-36-37 7-8-9-...-36-37-38 ... 14-15-16-...43-44-45 15-16-17-...-44-45-46 ... 30-31-32-...-59-60-61 31-32-33-...-60-61-62
1
No
7 ... 14 15 ... 30 31
24
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive strength during testing. See Table 4 for additional information. Table 4: Drive Strength BCR[5] 0 0 1 1 BCR[4] 0 1 0 1 Drive Strength Full 1/2 (default) 1/4 Impedance Typ ( 25~30 50 100 Reserved ) Use Recommendation CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid(See Figure 16).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 16: WAIT Configuration During Burst Operation
CLK
WAIT
BCR[8] = 0 Data Valid in current cycle
WAIT initial latency A/DQ[15:0] D0 D1 D2
BCR[8] = 1 Data Valid in next cycle D3
End of row Don't Care
Note: Non-default BCR setting: WAIT active LOW.
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes, see Table 5 and 6 on pages 26 and 27, respectively, and Figure 17 and 18 in page 27, respctively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter(See Table 6 on page 27 and Figure 18 on page 27). Table 5: Variable Latency Configuration Codes BCR[13:11] 010 011 100 Others Latency Configuration Code 2 (3 clocks) 3 (4 clocks)-default 4 (5 clocks) Reserved Latency1 Normal 2 3 4 Refresh Collision 4 6 8 Max Input CLK Frequency (MHz) 133 66(15ns) 104 66(15ns) 83 52(19.2ns) 83(12ns) -
104(9.62ns) 104(9.62ns) 133(7.5ns) -
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
26
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision)
CLK
VIH VIL VIH VIL VIH
A[21:16]
Valid Address
ADV#
VIL
Code 2 A/DQ[15:0]
VIH VIL VIH VIL
Valid Address
Code 3 (default)
D0
D1
D2
D3
D4
D5
D6
D7
A/DQ[15:0]
Valid Address
Code 4
D0
D1
D2
D3
D4
D5
D6
D7
A/DQ[15:0]
VIH VIL
Valid Address
D0
D1
D2
D3
D4
D5
D6
Don't Care
Undefined
Table 6: Fixed Latency Configuration Codes BCR[13:11] 010 011 100 101 110 000 Others Latency Configuration Code 2 (3 clocks) 3 (4 clocks)-default 4 (5 clocks) 5 (6 clocks) 6 (7 clocks) 8 (9 clocks) Reserved Latency Count (N) Normal 2 3 4 5 6 8 -Max Input CLK Frequency (MHz) 133 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 104(9.62ns) 133(7.5ns) 104 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 104(9.62ns) 83 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 83(12ns) -
Figure 18: Latency Counter (Fixed Latency)
N-1 Cycles CLK
VIH VIL
Cycle N
tAA
VIH
A[20:16]
VIL
Valid Address tAADV
VIH
ADV#
VIL VIH VIL VOH
tCO tACLK Valid Output tSP tHD Valid Output Valid Output Valid Output Valid Output
CE#
A/DQ[15:0] (READ) VOL A/DQ[15:0] VOH (WRITE) VOL
Valid Address Burst Identified (ADV# = LOW)
Valid Input
Valid Input
Valid Input
Valid Input
Valid Input Undefined
Don't Care
27
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
REFRESH CONFIGURATION REGISTER
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Figure 19 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with A/DQ = 0000h on the third cycle. Figure 19: Refresh Configuration Register Mapping
A[20] A[19:18] A[17:16] A/DQ [15:7] A/DQ 6 A/DQ 5 A/DQ 4 A/DQ 3 A/DQ 2 A/DQ 1 A/DQ 0
20 Reserved
19-18 Register Select
17-16 Reserved
15~7 Reserved
6
5 Ignored
4
3 Reserved
2
1 PAR
0
All must be set to "0"
All must be set to "0"
Setting is ignored (Default 001b)
Must be set to "0"
RCR[19] 0 1 0
RCR[18] 0 0 1
Register Select Select RCR Select BCR Select DIDR
RCR[2] 0 0 0 0 1 1 1 1
RCR[1] 0 0 1 1 0 0 1 1
RCR[0] 0 1 0 1 0 1 0 1
Refresh Coverage Full array (default) Bottom 1/2 array Bottom 1/4 array Bottom 1/8 array None of array Top 1/2 array Top 1/4 array Top 1/8 array
Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written.
28
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh)
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map(See Table 7 and Table 8). Table 7: Address Patterns for PAR (RCR[4] = 1) RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1 Active Section Full Die One-half die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die Address Space 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 0 100000h-1FFFFFh 180000h-1FFFFFh 1C0000h-1FFFFFh Size 2 Meg x 16 1 Meg x 16 512 K x 16 256 K x 16 0 Meg x 16 1 Meg x 16 512 K x 16 256 K x 16 Density 32Mb 16Mb 8Mb 4Mb 0Mb 16Mb 8Mb 4Mb
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8 describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A/DQ = 0002h on the third cycle. Table 8: Device Identification Register Mapping Bit Field
Field name
DIDR[15]
Row Length Length Bit Setting 0b
DIDR[14:11]
Device version Version 2nd Bit Setting 0001b
DIDR[10:8]
Device density Density 32Mb Bit Setting 001b
DIDR[7:5]
CellularRAM generation Generation CR 1.5 Bit Setting 010b
DIDR[4:0]
Vendor ID Vendor EMLSI Bit Setting 01010b
Options
128 words
29
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
ELECTRICAL CHARACTERISTICS
Table 9: Absolute Maximum Ratings Parameter
Voltage to any pin except Vcc, VccQ relative to Vss Voltage on Vcc supply relative to Vss Voltage on VccQ supply relative to Vss Storage temperature (plastic) Operating temperature (case) Wireless Soldering temperature and time: 10s (solder ball only)
Rating
-0.3V to VccQ + 0.3V -0.2V to +2.45V -0.2V to +2.45V -55C to +150C -30C to +85C +260C
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 10: Electrical Characteristics and Operating Conditions Wireless Temperature (-30C < TC < +85C) Description
Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or chip disabled
Conditions
VCC VCCQ VIH VIL VOH VOL ILI ILO
Symbol
Min
1.7 1.7 VCCQ - 0.4 -0.20 0.80 X VCCQ
Max
1.95 1.95 VCCQ + 0.2 0.4
Unit Notes
V V V V V 1 2 3 3
0.20 X VCCQ 1 1
V
A A Unit Notes
mA mA mA mA mA mA mA mA mA mA 4 4 4 4
Operating current
Asynchronous random READ/WRITE Initial access, burst READ/WRITE
Conditions
ICC1
Symbol
70ns 133MHz ICC2 104MHz 83MHz
Typ
Max
25 40 35 30 35 30 25 40 35 30 140
VIN = VCCQ or 0V chip enabled, IOUT = 0 Continuous burst READ ICC3R
133MHz 104MHz 83MHz 133MHz
Continuous burst WRITE
ICC3W
104MHz 83MHz Standard
A A A
5, 6
Standby current
VIN = VCCQ or 0V, CE# = VCCQ
ISB
Low Power Low-Low Power
TBD
120 100
Note: 1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. 3. BCR[5:4] = 01b (default setting of one-half drive strength). 4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (max) values measured with PAR set to FULL ARRAY and at +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode. 6. ISB (typ) is the average ISB at 25C and VCC = VCCQ = 1.8V. This parameter is verified during characterization, and is not 100% tested.
30
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 11: Capacitance Description
Input Capacitance Input/Output Capacitance(A/DQ) Tc = = +25C; f = 1 MHz; VIN = 0V
Conditions
Symbol
CIN CIO
Min
2.0 3.0
Max
6 6.5
Unit Notes
pF pF 1 1
Note: 1. These parameters are verified in device characterization and are not 100% tested.
Figure 20: AC Input/Output Reference Waveform
VccQ Input1 VssQ VccQ/22 Test Points VccQ/23 Output
Note: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2.
Figure 21: AC Output Load Circuit
Test Points 50
DUT
VccQ/2 30pF
Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
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Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
TIMING REQUIREMENTS
Table 12: Asynchronous READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Parameter
Address access time ADV# access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output Chip select access time CE# LOW to ADV# HIGH Chip disable to DQ and WAIT High-Z output Output enable to valid output OE# LOW to WAIT valid Output disable to DQ High-Z output Output enable to Low-Z output ADV# pulse width
Symbol
tAA tAADV tAVH tAVS tBA tBHZ tCO tCVS tHZ tOE tOEW tOHZ tOLZ tVP
Min
Max
70 70
Unit
ns ns ns ns
Notes
2 5 70 7 70 7 7 20 1 7.5 8 3 5
ns ns ns ns ns ns ns ns ns ns 1 2 1 1
Note: 1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
32
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 13: Burst READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Parameter
Address access time (fixed latency) ADV# access time (fixed latency) Burst to READ access time (variable latency) CLK to output delay Address hold from ADV# HIGH(fixed latency) Burst OE# LOW to output delay CE# HIGH between subsequent burst or mixed mode operations Maximum CE# pulse width CLK period Chip select access time (fixed latency) CE# setup time to active CLK edge Hold time from active CLK edge Chip disable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT valid Output HOLD from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge
Symbol
tAA tAADV tABA tACLK tAVH tBOE tCBPH tCEM tCLK tCO tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP 3 2 2 3 5 2
133MHz
Min Max 70 70 35.5 5.5 2 20 5 4 7.5 70 2.5 1.5 7 1.2 5.5 2 2 3 7 3 3 3 2
104MHz
Min Max 70 70 35.9 7 2 20 6 4 9.62 70 4 2 8 1.6 7 2 2 4 8 3 3 12
83MHZ
Min Max 70 70 45 9
Unit Notes
ns ns ns ns ns 20 ns ns 4 1 1
s
ns
70
ns ns ns
8 1.8 9
ns ns ns ns ns
2
8
ns ns ns
2 3
Note: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
33
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 14: Asynchronous WRITE Cycle Timing Requirements Parameter
Address and ADV# LOW setup time to WE# LOW Address HOLD from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# HIGH between subsequent async operations CE# LOW to ADV# HIGH Chip enable to end of WRITE Data HOLD from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output ADV# pulse width ADV# setup to end of WRITE WRITE to DQ High-Z output WRITE pulse width WRITE recovery time
Symbol
tAS tAVH tAVS tAW tBW tCPH tCVS tCW tDH tDW tHZ tVP tVS tWHZ tWP tWR
Min
0 2 5 70 70 5 7 70 0 20
Max
Unit
ns ns ns ns ns ns ns ns ns ns
Notes
7 5 70 8 45 0 4000
ns ns ns ns ns ns
1
1 2
Note: 1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 2. WE# Low time must be limited to tCEM (4s).
34
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 15: Burst WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time
to WE# LOW Address HOLD from ADV# HIGH(fixed latency)
Symbol tAS
tAVH 0 2 5
133MHz
Min Max
104MHz
Min 0 2 5 4 4 9.62 3 2 7 8 1.6 7 2 3 3 2 3 3 12 4 2 Max
83MHZ
Min 0 2 6 4 Max
Unit Notes
ns ns ns 2 2 1
CE# HIGH between subsequent burst or mixed mode operations Maximum CE# pulse width Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output CLK rise or fall time Clock to WAIT valid
Output HOLD from CLK
tCBPH tCEM tCLK tCSP tHD tHZ tKHKL tKHTL
tKOH
s
ns ns ns
7.5 2.5 1.5
8 1.8 9
ns ns ns ns ns ns
3
1.2 5.5 2 3 2
CLK HIGH or LOW time Setup time to activate CLK edge
tKP tSP
Note: 1. tAS required if tCSP > 20ns. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 3. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
35
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
TIMING DIAGRAMS
Figure 22: Initialization Period
Vcc(MIN) Vcc, VccQ = 1.7V tPU
Device ready for normal operation
Table 16: Initialization Timing Parameters Parameter
Initialization period (required before normal operations)
Symbol
tPU
Min
Max
150
Unit s
Figure 23: Asynchronous READ A[20:16]
VIH VIL
Valid Address
tAA tAVS tAVH
VIH
ADV#
VIL
tAADV tVP tCVS tHZ
VIH
CE# V
IL
tCO tBA tBHZ
VIH
LB#/UB#
VIL
VIH
tOE
tOHZ
OE#
VIL
VIH
WE#
tOLZ tAVS tAVH
VOH VOL
VIL VIH VIL
A/DQ[15:0]
Valid address
tAA
Valid Output
tHZ
tOEW
WAIT
VOH VOL
High-Z
High-Z
Don't Care
Undefined
36
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 24: Single-Access Burst READ Operation - Variable Latency
tCLK
VIH
tKP
tKP
CLK
VIL
tKHKL tSP tHD
VIH
A[20:16]
Valid Address
tSP tHD tHD tCSP tABA tCEM tHZ
VIL VIH VIL VIH
ADV#
CE#
VIL VIH
tBOE tSP tHD tOLZ
tOHZ
OE#
VIL VIH
WE#
VIL VIH
tSP
tHD
LB#/UB#
VIL VIH
tSP
tHD
VOH
tACLK High-Z
VOL
tKOH High-Z
A/DQ[15:0]
VIL VOH
Valid Address
High-Z
Valid Output
tKOH High-Z tKHTL
WAIT
VOL
tKHTL
READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
37
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 25: 4-Word Burst READ Operation - Variable Latency
tKHKL
VIH
tCLK
tKP
tKP
CLK
VIL VIH
tSP
tHD
A[20:16]
VIL VIH
Valid Address
tSP tCSP tHD
ADV#
VIL VIH
tABA tCEM
tHD
tCBPH tHZ
CE#
VIL VIH
tBOE tSP tHD tOLZ tOHZ
OE#
VIL VIH
WE#
VIL VIH
tSP tHD
VOH VOL
tHD
LB#/UB# A/DQ[15:0]
VIL VIH VIL VOH
tSP
tACLK
Valid Output
tKOH
Valid Output Valid Output Valid Output
Valid address
High-Z
Note 3 High-Z Note 2 High-Z
tKOH
WAIT
VOL
tKHTL
tKHTL
READ Burst Identified (WE# = HIGH)
Notes : 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT Will remain de-asserted even if CE# remains LOW past the end of the defined burst length. 3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
Don't Care
Undefined
38
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 26: Single-Access Burst READ Operation - Fixed Latency
tCLK
VIH
tKP
tKP
CLK
VIL VIH
tSP Valid Address tAVH tSP tHD tAADV tCEM tCSP tCO
tKHKL
A[20:16]
VIL VIH
tAA
ADV#
VIL
tHD tHZ
VIH
CE#
VIL VIH
tBOE tOLZ
tOHZ
OE#
VIL VIH
tSP
tHD
WE#
VIL VIH
tSP tAVH
VOH VOL
tHD
UB#/LB#
VIL
tSP
VIH
tACLK
tKOH
Valid Output
A/DQ[15:0]
Valid Address
VIL VOH
High-Z
tKOH High-Z
WAIT
VOL
High-Z tKHTL tKHTL
READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
39
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 27: 4-Word Burst READ Operation - Fixed Latency
tKHKL
VIH
tCLK
tKP
tKP
CLK
VIL VIH
tSP
A[20:16]
VIL
Valid Address
tAVH tSP tHD tAADV tCSP tCO tBOE tSP tHD tOLZ tOHZ tAA
VIH
ADV#
VIL
tCEM tHD tCBPH tHZ
VIH
CE#
VIL VIH
OE#
VIL VIH
WE#
VIL VIH
tSP tACLK
VOH VOL Valid Output
tHD
UB#/LB#
VIL
tSP
VIH
tAVH
tKOH
Valid Output Valid Output Valid Output
A/DQ[15:0]
VIL VOH
Valid address
High-Z
Note 3 High-Z Note 2 High-Z
tKOH
WAIT
VOL
tKHTL
tKHTL
READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
Notes : 1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length. 3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
40
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 28: Burst READ Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL VIH
tCLK
A[20:16]
VIL VIH
ADV#
VIL VIH
UB#/LB#
VIL VIH
tHD Note 2
tCSP
CE#
VIL VIH
OE#
VIL VIH
WE# A/DQ[15:0]
VIL VOH VOL VOH VOL Valid Output Valid Output
End of row
tKHTL
tHZ
tHZ High-Z
WAIT
tKOH Don't Care Undefined
Notes : 1. Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW; WAIT asserted during delay. 2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( befor the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1 ).
41
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 29: Burst READ Row Boundary Crossing
CLK
VIH VIL
tCLK
A[20:16] ADV#
VIH VIL VIH VIL VIH
UB#/LB#
VIL VIH VIL
CE#
OE#
VIH VIL VIH VIL
WE#
tSP
VOH
tHD
End of row
Valid output Valid output Valid out
A/DQ[15:0]
Valid output VOL VOH
tKTHL Note 2 tKOH
tKTHL
WAIT V OL
tKOH
Don't Care Note: 1. Nondefault BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
42
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 30: Asynchronous WRITE
VIH
A[20:16]
Valid Address VIL
tAVS tVP tAS tAS tCVS
tAVH tVS
ADV#
VIH VIL
tAW tCW
VIH
CE#
VIL VIH
tBW
UB#/LB#
VIL VIH
OE#
VIL VIH
tWP tAS tAVS tAVH tDW
Valid Input
WE#
VIL VIH VIL
tDH
A/DQ[15:0]
Valid Address
WAIT
VOH VOL
tAW
High-Z
Don't Care
43
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 31: Burst WRITE Operation - Variable Latency Mode
tCLK tKHKL tKP tKP
CLK
VIH VIL VIH
tSP
tHD
A[20:16]
Valid Address VIL VIH
tAS3 tSP tAS
3
ADV#
tHD tSP tHD tHD tCEM Note4 tCBPH
VIL VIH
UB#/LB# CE#
VIL VIH VIL VIH
tCSP
OE#
VIL VIH
tSP
tHD
WE#
VIL VIH VIL VOH
tAS3
tHD
Valid Address
tSP
D1
tHD
D2 D3 D0
A/DQ[15:0]
tSP High-Z
tKHTL Note 2
tKHTL
tHZ High-Z
WAIT
VOL
tKOH
WRITE Burst Identified (WE# = Low)
Don't Care Note: 1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay, burst length 4, burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). tAS required if tCSP > 20ns. 3. 4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
44
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 32: Burst WRITE Operation - Fixed Latency Mode
tCLK tKHKL tKP tKP
CLK
VIH VIL VIH Valid Address VIL VIH
tSP
A[20:16]
tAS3 tSP tAS3 tHD
tAVH
ADV#
VIL VIH
tSP
tHD tHD tCBPH Note 4
UB#/LB#
VIL VIH
tCSP
CE#
tCEM
VIL VIH
OE#
VIL VIH
tSP
tHD
WE# A/DQ[15:0] WAIT
VIL VIH VIL VOH
tAS3
Valid Address
tAVH
tSP
D1
tHD
D2 D3 D0
tSP High-Z
tKHTL Note2
tKHTL
tHZ High-Z
VOL
tKOH Don't Care
WRITE Burst Identified (WE# = LOW)
Note: 1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2(3 clocks), WAIT active LOW, WAIT asserted during delay, burst length 4, burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). 3. tAS required if tCSP > 20ns. 4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
45
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL VIH
tCLK
A[20:16]
VIL VIH
ADV#
VIL VIH
UB#/LB#
VIL VIH
tHD Note 2
tCSP
CE#
VIL VIH
OE#
VIL VIH
WE#
VIL VIH
tSP
tHD
Valid Intput
A/DQ[15:0]
VIL VOH
Valid Intput
End of row tKOH tKHTL
tHZ
tHZ High-Z
WAIT
VOL
Don't Care
Note: 1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).
46
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 34: Burst WRITE Row Boundary Crossing
CLK
VIH VIL VIH
tCLK
A[20:16]
VIL
VIH
ADV#
VIL VIH
UB#/LB# CE# OE#
VIL VIH VIL VIH VIL
WE#
VIH VIL VIH
tSP
tHD
Valid input
End of row
Valid input Valid output Valid output
A/DQ[15:0] WAIT
VIL VOH VOL
Valid input
tKTHL tKOH Note 2
tKTHL
tKOH
Don't Care
Note: 1. Nondefault BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
47
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 35: Burst WRITE Followed by Burst READ
tCLK
CLK
VIH VIL VIH VIL
tSP tHD
Valid Address
tSP tHD
Valid Address
A[20:16]
ADV#
VIH VIL VIH
tSP tHD tHD
tSP tHD
tSP
UB#/LB#
VIL VIH
tCSP
tHD tCBPH
Note 2
CE#
VIL VIH
tCSP
tOHZ
OE#
VIL VIH
tSP tHD tSP tHD
D0 D1 D2 D3
tSP tHD
WE# A/DQ[15:0]
VIL VIH VIL VOH VOL
tSP tHD
Valid Output
tSP tHD
Valid Address
tBOE
VOH VOL
Valid Output
tKOH
Valid Output Valid Output Valid Output
WAIT
tACLK High-Z High-Z
Don't Care
Undefined
Note: 1. Nondefault BCR settings for burst WRITE followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
48
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 36: Asynchronous WRITE Followed by Burst READ
tCLK
VIH
CLK
VIL VIH
tSP
Valid Address
tHD
A[20:16]
Valid Address
VIL VIH
tAVS tVP tAS
tAVH
tSP
tHD
ADV#
VIL VIH
tBW
tSP
tHD
UB#/LB#
VIL VIH VIL VIH
tCBPH tCW Note 2
tCSP
CE#
tOHZ
OE#
VIL VIH VIL VIH
tWP tWC tAS
Valid Address Data
tSP tHD
WE#
tSP
tHD
VOH VOL
tBOE
Valid Output Valid Output Valid Output Valid Output
A/DQ[15:0]
Valid Address
VIL VOH
tAVS
tAVH
tDW
tDH
WAIT
tKHTL
tACLK
VOL
tKOH
High-Z
Don't Care
Undefined
Note: 1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. When the divice is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
49
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 37: Burst READ Followed by Asynchronous WRITE
tCLK
CLK
VIH VIL VIH
tSP
tHD
Valid Address
A[20:16]
Valid Address VIL
tAVS tSP tHD tVP tAS tCSP tHD tCBPH tHZ tOHZ Note 2
tAVH
tVS
VIH
ADV#
VIL
CE#
VIH VIL
tAW tCW
OE#
VIH VIL
tBOE tSP tHD tOLZ
tAS
tWP
tWPH
WE#
VIH VIL VIH VIL VIH
tSP
tHD tAS
tBW
UB#/LB#
tSP
tHD
VOH VOL
tACLK
tKOH
VIH Valid Output VIL
tAVS
tAVH
tDW
tDH
A/DQ[15:0]
Valid Address VIL VOH
Valid Address
Valid Input
tKOH
WAIT
High-Z VOL
High-Z
tKHTL
tKHTL Don't Care Undefined
READ Burst Identified (WE# = HIGH)
Notes: 1. Nondefault BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the device is transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
50
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 38: Asynchronous WRITE Followed by Asynchronous READ
A[20:16]
VIH Valid Address VIL
Valid Address
tAVS tAS
tAVH tAW tVS tWR tBW
tAVS
tAVH
tAA tAADV
VIH
ADV#
VIL VIH
tVP
tAS
tVP
tCVS tBA tCO tBHZ
UB#/LB#
VIL VIH VIL VIH VIL
tCVS tCW
tCPH
tHZ
CE#
Note 1
tOLZ
tOHZ tOE
OE# WE#
tWP tAS
VIH VIL
tAW
Valid Input Valid Address
tAA
VOH VOL Valid Output
A/DQ[15:0]
VIH Valid Address VIL VOH
tAVS
tAVH
tDS
tDH
High-Z
tAVS
tAVH
tOEZ
tHZ
WAIT
VOL
Don't Care
Undefined
Note: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.
51
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X X - XX XX
1. EMLSI Memory 2. Device Type 3. Density 4. Function 5. Technology 6. Operating Voltage
1. Memory Component 2. Device Type 6 ---------------------- Low Power SRAM 7 ---------------------- STRAM C ---------------------- CellularRAM 3. Density 4 ----------------------- 4M 8 ----------------------- 8M 16 --------------------- 16M 32 --------------------- 32M 64 --------------------- 64M 28 --------------------- 128M 4. Function 2 ----Multiplexed async. 3-----Demultiplexed async. with page mode 4-----Demultiplexed async. with direct DPD 5-----Multiplexed sync. 6-----Optional mux/demuxed sync. 5. Technology S ----------------------- Single Transistor & Trench Cell 6. Operating Voltage V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit
12. Power 11. Speed 10. PKG 9. Option 8. Version 7. Organization
8. Version Blank ----------------- Mother die A ----------------------- 2'nd generation B ----------------------- 3'rd generation C ----------------------- 4'th generation D ----------------------- 5'th generation 9. Option Blank ---- No optional mode H ----------- Demultiplexed with DPD J ------------ Demultiplexed with DPD & RBC K ------------ Multiplexed with RBC L ------------ Multiplexed with DPD & RBC 10. Package Blank ---------------------- Wafer S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 P ---------------------- 48 FPBGA Z ---------------------- 52 FPBGA Y ---------------------- 54 FPBGA V ---------------------- 90 FPBGA 11. Speed (@async.) 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 12. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-Free&Green) L ---------------------- Low Power 52

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